System for maintaining the stability of a programmable frequency multiplier
US6657463B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 2001 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Jun 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable frequency multiplier receives data representing a desired multiplication ratio from a first configuration register. The ratio data is transferred to the frequency multiplier concurrently with the generation of an internal delayed reset signal which holds all configuration registers in a reset condition until the frequency multiplier achieves a locked state. The configuration registers are dependent upon the internal clock signal generated by the frequency multiplier for proper operation. By causing the configuration registers to renew operation only after the stable frequency multiplier operation the danger of corrupting the information in the configuration registers is minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.