Method and circuit to reduce jitter generation in a PLL using a reference quadrupler, equalizer, and phase detector with control for multiple frequencies
US6657464B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2002 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Apr 25, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low-jitter phase-locked loop (PLL) circuit includes a reference signal generator and a PLL. The reference signal generator is configured to quadruple a frequency of a first reference signal to produce a second reference signal. The PLL includes a filter coupled in series with a voltage controlled oscillator (VCO), and a frequency phase detector configured to generate a first error signal based on a frequency difference between the second reference signal and a first divided VCO output signal. The PLL further includes a phase detector configured to generate a second error signal based on a phase difference between the second reference signal and a second divided VCO output signal at each rising and falling transition of the second reference signal. The PLL further includes a multiplexer configured for initially receiving the first error signal until the frequencies of the first divided VCO output signal feedback signal and the second reference signal match, and thereafter for receiving the second error signal, and to provide the first or second error signal to the filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.