Dynamic graphics and/or video memory power reducing circuit and method
US6657634B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 1999 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Feb 25, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method dynamically controls the graphics and/or video memory power dynamically during idle periods of the memory interface during active system modes. In one embodiment, a memory request detector generates memory request indication data, such as data representing whether memory requests have been received within a predetermined time, based on detection of graphics and/or video memory requests during an active mode of the display system operation. A dynamic activity based memory power controller analyzes the memory request indication data and controls the power consumption of the graphics and/or video memory based on whether memory requests are detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.