ESD protection circuit for mixed-voltage I/O by using stacked NMOS transistors with substrate triggering technique

US6657835B2 · kind B2 · utility

Assignee

• Silicon Integrated Systems Corp. · TW

Inventors

• Ming-Dou Ker · Hsinchu, TW
• Chien-Hui Chuang · Taipei, TW
• Wen-Yu Lo · Taichung, TW

Key dates

• Filing date: Jun 7, 2001
• Grant date: Dec 2, 2003
• Expiry date: Jan 1, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002

Abstract

An ESD protection circuit for Mixed-Voltage I/O by using stacked NMOS transistors with substrate triggering technique is disclosed. The ESD protection circuit contains a set of stacked NMOS transistors with a first NMOS transistor and a second NMOS transistor, a parasitic lateral bipolar transistor, a substrate current generating circuit, and a parasitic substrate resistor. The drain of the first NMOS transistor connects to an I/O pad. The gate of the first NMOS transistor connects to a first working voltage. The source of the first NMOS transistor connects to the drain of the second NMOS transistor. The gate of the second NMOS transistor connects to an internal circuit. The source of the second NMOS transistor connects to a second working voltage. The collector of the parasitic lateral bipolar transistor connects to the drain of the first NMOS transistor and its emitter connects to the source of the second NMOS transistor. A first terminal of the substrate current generating circuit connects to the I/O pad, a second terminal connects to the second working voltage, and a third terminal connects to the substrate of the lateral bipolar transistor, so that a triggering current is sent…