Semiconductor device with low power consumption memory circuit
US6657911B2 · kind B2 · utility
65Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2002 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Oct 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a system LSI consolidating a logic circuit and an SRAM circuit. More specifically, the present invention relates to a semiconductor device which can reduce a leakage current and the power consumption in the standby state.The logic circuit in the system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing a leakage current. At the same time, the SRAM circuit controls a substrate bias to reduce the leakage current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.