Glitcher system and method for interfaced or linked architectures
US6657968B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 1999 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | May 18, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1816
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A serial differential link glitcher system and method which allow for verification of error recovery by an interfaced or linked architecture system. The system and method provide accurate, reliable, and more assured fault simulation, such as noisy interface and dirty link simulations, within an interfaced or linked architecture system for verification of such error recovery and verifies and checks data at a lower level between interfaced devices. The system and method verify disparity errors between interfaced devices and also perform verification of error recovery between electrically linked devices or optically linked devices. At least two devices are coupled together by communication lines. Normal mode allows for normal operation of and normal communication between the at least two devices, and glitch mode provides fault simulation and disparity errors and phase inversion between the at least two devices for testing error recovery of the system. Proper polarity of the communication lines is maintained between the at least two devices when the system is in normal operation mode. The polarity of the communication lines between the at least two devices is switched and inverted when…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.