Jitter buffer management
US6658027B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 1999 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Aug 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0632
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In order to compensate for rate mismatches between near end (receiving) and far end (transmitting) devices, intelligent jitter buffer management is implemented by apparatus comprising: a data interface for receiving frames from a data network; a jitter buffer for temporarily storing said frames; a detector for detecting frames which satisfy a criteria; and a buffer manager for controlling the frames stored in said jitter buffer based on the condition of said buffer and on frames which satisfy said criteria. The criteria can include silence frames or frames received with errors. The condition can include a high water mark (high threshold), and a low water mark (low threshold). If the far end transmitter transmits at a faster rate than the near end receiver, the jitter buffer will eventually become full beyond the high water mark, in which case frame(s) which satisfy the criteria will be deleted. If the far end transmitter transmits at a slower rate than the near end receiver, the jitter buffer will eventually become depleted below the low water mark, in which case silence frame(s) will be inserted after received silence frames.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.