Fast chainable carry look-ahead adder
US6658446B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2000 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Oct 2, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A chainable adder receives bits (A, B, C) to give complementary sum outputs (SO, SO*) and carry outputs (CO, CO*).A first stage has differential pairs (P1, P2, P3) receiving bits (A, B, C), respectively, and complements (A*, B*, C*), respectively. The pairs have common output arms and are powered by an identical current (I). First and second output arms include resistors (R1, R2, R3) and (R4, R5, R6), respectively, connected-in-series to a reference potential (M). The resistors define intermediate nodes (A1, A2, A3) in the first arm, (B1, B2, B3) in the second arm. Carry outputs are taken at nodes (A2, B2).A second stage has differential pairs (P4, P5, P6) whose inputs are connected to nodes (A1, B3) for pair (P4), (A2, B2) for pair (P5), and (A3, B1) for pair (P6). Pairs (P4, P6) each have a common arm with the pair (P5) and a non-common arm. The sum outputs are constituted by a combination, according to an “OR” function, of logic states on the non-common arm of one of pairs (P4, P6) and on the common arm of another of pairs (P4, P6).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.