Semiconductor-on-insulator annealing method
US6660606B2 · kind B2 · utility
20Cited by
12References
12Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 27, 2001 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Mar 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The number of defects (HF defects) in the SOI layer of an SOI substrate is reduced. In an annealing method of annealing an SOI substrate in a reducing atmosphere at a temperature equal to or less than the melting point of a semiconductor, annealing is executed in a state wherein a flow of a reducing atmospheric gas parallel to the surface of the SOI substrate is generated near this surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.