Circuit board having solder bumps
US6660944B1 · kind B1 · utility
21Cited by
7References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 1997 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Apr 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/043
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit board having a plurality of solder bumps is provided. The solder bumps are flattened and leveled at the tops so that the coplanarity of the solder bumps is 0.5 &mgr;m or less per 1 mm. The flattened and leveled tops of the solder bumps are formed by cold pressing, hot pressing or grinding. Method of forming such solder bumps and jigs used for carrying out such methods are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.