Integrated circuit including field effect transistor and method of manufacture
US6661024B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Jul 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/621
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An integrated circuit (100, 200, 300, 400) that includes a field effect transistor (102, 202, 302, 402) is fabricated by forming an organic semiconductor channel (112, 216, 308, 418) on one substrate (106, 204), forming device electrodes (114, 116, 110, 208, 210, 212) on one or more other substrates (104, 108, 206), and subsequently laminating the substrates together. In one embodiment, a dielectric patch (214) that functions as a gate dielectric is formed on one of the substrates (204, 206) prior to performing the lamination. Lamination provides a low cost route to device assembly, allows for separate fabrication of different device structures on different substrates, and thins various device layers resulting in improved performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.