DMOS transistor protected against polarity reversal
US6661056B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Sep 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/157
Abstract
The present invention relates to a circuit configuration for protecting against polarity reversal of a DMOS transistor.A charge carrier zone (30) is provided, situated in the drift zone (14) of DMOS transistor (10), made up of individual partial charge carrier zones (32) situated at a distance from one another and connected to one another in a conducting manner, the charge carrier zone (30) having an opposite charge carrier doping from that of the drift zone (14), and being able to be acted upon by a potential that is negative with respect to a potential present at a drain terminal (24) of the DMOS transistor (10), so that a short-circuit current is prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.