Lateral insulated gate bipolar PMOS device
US6661059B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Sep 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D12/421
Abstract
A lateral insulated gate bipolar PMOS device includes a semiconductor substrate, a buried insulating layer and a lateral PMOS transistor device in an SOI layer on the buried insulating layer having a source region of p-type conductivity. A lateral drift region of n-type conductivity is provided adjacent the body region, and a drain region of the p-type conductivity is provided laterally spaced from the body region by the drift region. An n-type conductivity drain region is formed of a shallow n-type contact surface region inserted into a p-inversion buffer. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being insulated from the body region and drift region by an insulation region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.