Multi-phase edge rate control for SCSI LVD
US6661271B1 · kind B1 · utility
5Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | May 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus having a plurality of serially cascaded delay cells each configured to generate a phase of a multi-phase signal and an intermediate signal, where (i) each of the delay cells is generally configured to respond to a bias signal and one of the intermediate signals and (ii) a first of the delay cells is generally configured to respond to an input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.