One-by-N switch matrix
US6661308B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 19, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Aug 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/13106
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A 1-by-N switch matrix (10) includes at least two ranks of switches (12-1, 12-2-1, 12-2-2, 12-3-1, . . . , 12-3-4, 12-4-1, . . . , 12-4-8, and 12-5-1, . . . , 12-5-16; 112-1, 112-2-1, 112-2-2, 112-3-1, . . . , 112-3-4, 112-4-1, . . . , 112-4-8, and 112-5-1, . . . , 112-5-8). Each switch has first, second and third terminals (1, 2, 3). A first state of each switch couples the first terminal (1) to the second terminal (2) and a second state of each switch couples the first terminal (1) to the third terminal (3). The second (2) and third (3) terminals of each switch (12-1, 12-2-1, 12-2-2, 12-3-1, . . . 1., 2-3-4; 112-1, 112-2-1, 112-3-3 and 112-3-4) of each rank (-1-, -2-, -3-) above the next to lowest rank (-4- or -3-) are coupled to first terminals (1) of respective switches (12-4-1, . . . , 12-4-8 and 112-3-1, 112-3-2, 112-4-5, 112-4-8) in the next lower rank (-2-, -3-, -4-). The second (2) and third (3) terminals of each switch (12-4-1, 12-4-8 and 112-3-1, 112-3-2, 112-4-5,. . . , 112-4-8) in the next to lowest rank (-4- or -3-) are coupled to the second terminals (2) of respective switches (12-5-1, 12-5-16; 112-4-1, 112-4-4 and 112-5-1, . . . , 112-5-8) in the lowest rank (-5- or…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.