Circuit architectures and methods for A/D conversion
US6661365B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Apr 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An array of transistor circuits is fabricated so that each transistor circuit in an array of transistor circuits has a switching threshold determined by intrinsic switching thresholds of at least one sensing transistor in a corresponding transistor circuit. The sensing transistors in a set of transistor circuits of the array can be fabricated to have common physical dimensions even though corresponding intrinsic switching thresholds of the transistor circuits can vary. Switching thresholds of the transistor circuits can vary based on an applied well bias voltage. Alternatively, the switching threshold of each transistor circuit can be set to a common value and a tapped delay line can be coupled to the transistor circuits. Consequently, an A/D converter device can be fabricated by coupling an encoder, and a calibration circuit if necessary, to the output of the array of transistor circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.