Layout method for bit line sense amplifier driver
US6661722B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Jul 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bit line sense amplifier is provided. The bit line sense amplifier includes a first sense amplifier block in which a plurality of first sense amplifiers for sensing and amplifying data of a bit line or a complementary bit line are laid out, and first drivers, which are arranged outside the plurality of first sense amplifiers, for pulling down the bit line or the complementary bit line to a first voltage level. The bit line sense amplifier further includes a second sense amplifier block with a plurality of second sense amplifiers and second drivers for pulling up the bit line or the complementary bit line to a second voltage level. By arranging the drivers outside the bit sense amplifiers, effects caused by variation in critical dimensions (CDs) of gates are minimized and the entire area of the bit line sense amplifier is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.