Radio receiver in CMOS integrated circuit
US6662003B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2000 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | May 9, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/28
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A single chip superhetrodyne AM receiver is disclosed herein. To compensate for process variations in the implementation of the IC, bias currents setting the operating conditions for various amplifiers and other components in the system are adjusted based on frequency control signals in a PLL circuit in the local oscillator. Since the magnitude of the control signal reflects the process variations, the bias currents are adjusted based on the control signal to offset these variations in other portions of the receiver. To further improve the signal to noise ratio of the receiver, the IF filter is tuned within a range so as not to include any integer multiple or integer divisor of the timing reference frequency. Various techniques are described for enabling a complete superhetrodyne AM receiver to be implemented on a single chip which receives an antenna input signal and outputs a digital data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.