Apparatus and system for blocking memory access during DMA transfer
US6662245B1 · kind B1 · utility
0Cited by
4References
3Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 25, 2001 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | May 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to an apparatus and system for selectively inhibiting access to a memory during a DMA block transfer. In accordance with one embodiment of the present invention, the system includes memory, a DMA engine, and logic configured so that when a control signal is asserted, the logic blocks the DMA engine's request for access to memory and generates an acknowledgment of the request, such that the DMA engine performs a DMA transfer without accessing data in memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.