Selective targeting of transactions to devices on a shared bus
US6662251B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2001 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Jun 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system in which bus signals are selectively modified to effectively isolate desired bus agents from the bus. The selective modification of bus signals may be determined from a stored table (permission table) indicating permitted and prohibited bus transaction initiator/target pairs. The permission table may be located in a dedicated device, such as a programmable logic array or application specific integrated circuit. Alternatively, the permission table may be integrated into the bus arbiter. The permission table may be used to provide a unique 1-bit signal to each bus agent indicating whether the corresponding bus agent is permitted to receive transactions from the current bus master. The permission bit may be routed to external gating circuitry associated with each bus agent. The gating circuitry may receive one or more bus control signals and may modify the control signals depending upon the state of the permission bit. In an embodiment in which the bus is a PCI bus, the gating circuitry may receive the FRAME# and GNT# signals for each bus agent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.