System architecture
US6662254B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2000 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Jan 25, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for a high capacity computer-based communications device is described. The system has an enhance backplane supporting a plurality of busses working independently of each other and each utilized for a different data type. The backplane supports a cPCI bus, a H.110 bus, and a StarLan bus. The system provides for increasing the capacity of the cPCI bus through bridging between two cPCI segments. A first serializer, operatively connected to the first cPCI segment, is used to receive data from a first PCI bus, serializes the data, and transfers the serial data stream to a second serializer which is operatively coupled to the second bus. The second serializer de-serializes the transferred data and transfers it to the second PCI bus. The backplane is utilized with a router and I/O modules to provide a device which combines traditional IP routing capabilities with a gateway for non-IP traffic to the IP network. A unique routing method is utilized to reduce the overhead associated with identifying data flows at the I/O module. The router receives the incoming datagrams and looks at the layer 3 and above headers to determine which I/O module to send the data to and to identify the d…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.