Method and apparatus for reducing power dissipation in finite field arithmetic circuits
US6662346B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Feb 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A finite field arithmetic circuit with reduced power dissipation has first and second circuit inputs. A first circuit transition probability of the first circuit input is calculated by applying a random input to the first circuit input and a constant input to the second circuit input. A second circuit transition probability of the second circuit input is calculated by applying a constant input to the first circuit input and a random input to the second circuit input. One of the first and second circuit inputs having a lower circuit transition probability is selected. A first time-varying rate that a first input signal to the arithmetic circuit varies is compared with a second time-varying rate that a second input signal to the arithmetic circuit varies. The input signal having a higher time-varying rate is selected and coupled to the selected one of the first and second circuit inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.