Method of repeater insertion for hierarchical integrated circuit design
US6662349B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | May 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of repeater insertion in a hierarchical integrated circuit includes defining an initial floorplan for a parent macro at a parent level in a hierarchical circuit design; passing outline and pin locations from the parent macro to a child macro sharing a common area with the parent macro; defining or modifying a floor plan for the child macro at a child level in the hierarchical circuit design in response to the outline and pin locations passed from the parent macro; passing physical restrictions in the child macro from the child macro to the parent macro; determining a location for a cell at the parent level of the hierarchical circuit design in an area of the parent macro shared by the child macro in response to the physical restrictions passed from the child macro; passing physical constraints in the parent macro associated with placement and routing of the cell from the parent level to the child macro; and generating an abstract representation for the child macro at the child level that includes an area cut out of the child macro corresponding to the location of the cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.