Semiconductor device and manufacturing method thereof
US6664145B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2000 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Jul 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6721
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.