Dielectric ARC scheme to improve photo window in dual damascene process
US6664177B1 · kind B1 · utility
12Cited by
6References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2002 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Jun 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, to improve the photolithography processing window of a multi-layered dual damascene process by using a dielectric anti-reflective coating, DARC, comprised of multiple layers of silicon oxynitride, SiON, with varying k, dielectric constant values and thickness, to reduce reflectivity and improve light absorption. By varying both the thickness and the dielectric constant of the layers, the optical properties of light absorption, refractive indices, and light reflection are optimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.