Pseudo-NMOS logic having a feedback controller
US6664813B2 · kind B2 · utility
4Cited by
7References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2002 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Mar 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01721
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pseudo-NMOS circuit includes a load PFET electrically connected between a power supply and an output node, and an NFET circuit having a plurality of inputs connected between the output node and ground. A feedback PFET is electrically connected between the power supply and the output node, in parallel with the load PFET, and is controlled by a signal at the output node of the pseudo-NMOS circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.