Distributed averaging analog to digital converter topology
US6664910B1 · kind B1 · utility
9Cited by
14References
42Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 13, 2003 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Jun 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/365
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.