Self calibrating register for source synchronous clocking systems
US6665218B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2001 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Jul 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A self calibrating register. In representative embodiments, registers for increasing source synchronous input/output (I/O) data rates by counteracting the inherent systematic sources of system mismatch are disclosed. Systematic sources of system mismatch between bit-line paths and devices, as for example printed circuit board path lengths, package trace lengths, on-chip clock routing, clock skew, device turn-on voltages, etc. are balanced out with respect to a reference clock signal by programmed delays of the data signals. The appropriate delays are obtained via phase shift detection circuitry and are then applied by control circuitry to signal delay circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.