Method and apparatus for reducing average power in RAMs by dynamically changing the bias on PFETs contained in memory cells
US6665227B2 · kind B2 · utility
73Cited by
2References
40Claims
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Key dates
| Filing date | Oct 24, 2001 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Jul 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for reducing power in SRAMS and DRAMS is implemented by dynamically controlling a voltage applied to Nwells containing PFETs used in memory cells. When a memory cell is in standby, the voltage applied to Nwells containing PFETs is increased in order to reduce leakage current. When a memory cell is being written, read, or refreshed, the voltage applied to Nwells containing PFETs is reduced in order to allow the memory cell to switch more quickly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.