Load testing apparatus, computer readable recording medium for recording load test program, fault diagnosis apparatus, and computer readable recording medium for recording fault diagnosis program
US6665268B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2000 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Feb 25, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY04S40/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a load testing apparatus, before the load test, three processor elements are combined, without overage or shortage, with a source processor element and a destination processor element as one pair, and the transmission time between the processor elements for each pair is measured. During the load test, packets are sent at a time from the source processor element to the corresponding destination processor element in the same pair, and the transmission time for each pair is measured. The transmission time measured for each pair in the load test is compared with a corresponding expected value data so as to evaluate the performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.