Digital receive phase lock loop with phase-directed sample selection
US6665362B1 · kind B1 · utility
0Cited by
5References
30Claims
0Family size
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Inventor
Key dates
| Filing date | Sep 14, 2000 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Jul 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
PLL error margin is improved by a half clock of the internal PLL clock by resolving the ambiguity between the two samples nominally centered about the pulse center point. This is achieved by intelligently choosing between the two samples nearest the pulse center by exploiting information from the phase error. Specifically, the choice is made depending upon the sign of the phase error. The result is that the margin of error of the PLL is improved by a half clock period, since on the average the choice between each one of the two samples represents half of the total one-clock resolution limit of the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.