Low-voltage transistor circuit for suppressing high-voltage surges in a telephone line interface circuit
US6665400B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 1999 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Apr 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M1/745
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A relay-less telephone line interface circuit is disclosed which incorporates a low-voltage transistor to suppress high-voltage, short-term voltage surges. Specifically, a low-voltage transistor such as a Central Semiconductor C2TA44, a Motorola MPSA42, or similar such transistors actually can withstand a high-voltage spike exceeding the manufacturers specified parameters. The present circuit exploits this undocumented feature by employing such a transistor in combination with a metal oxide varistor in order to provide adequate voltage surge protection for the interface circuit. Thus, a zenor diode is not necessary (avoiding on-hook problems) and the relay-less circuit still passes the FCC Part 68 test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.