Method and data processing system providing processor affinity dispatching
US6665699B1 · kind B1 · utility
50Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1999 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Sep 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor in a data processing system having multiple cache memories performs cache memory or processor module affinity dispatchin. Processes awaiting dispatch are stored in prioritized queues. Each queue has a priority chain, and a chain for each cache memory or processor module, with each chain containing processes ready for dispatch. The dispatcher checks the queues in priority order, starting with the priority chain for a queue, followed by the chain corresponding to the cache memory or processor module that the process last executed upon, followed by chains corresponding to other cache memories or processor modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.