Resetting a programmable processor
US6665795B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 6, 2000 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Jul 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a pipelined processor includes a reset unit that provides an output reset signal to at least one stage of the pipeline. The reset unit is adapted to detect at least a hard reset request, a soft reset request and an emulation reset request. The pipeline comprises N stages and the reset unit asserts the reset signal for at least N cycles of a clock after the reset request has been cleared. Each stage if the pipeline has a storage circuit for storing a corresponding valid bit. At least one of the storage circuits is cleared in response to the reset signal. In addition, the reset unit handles the reset request as a reset event having an assigned priority.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.