Method and arrangement for rapid silicon prototyping
US6665855B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2001 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Dec 28, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3308
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, the rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized subset of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.