Method to combine zero-etch and STI-etch processes into one process
US6667222B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2002 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | Jan 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for integrating the zero-etch and STI-etch processes into one process is described. An etch stop layer is deposited on a substrate. A mask is formed overlying the etch stop layer having a first opening for a planned alignment mark and having a second opening for a planned shallow trench isolation region. The etch stop layer is etched away within the first and second openings and the semiconductor substrate exposed within the first and second openings is etched into a first depth to form a first trench underlying the first opening and a second trench underlying the second opening. The first trench is covered and the second trench is etched into the semiconductor substrate to a second depth greater than the first depth. The second trench is filled to complete formation of a shallow trench isolation region wherein the first trench completes formation of an alignment mark in the fabrication of an integrated circuit device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.