Silicon wafers for CMOS and other integrated circuits
US6667522B2 · kind B2 · utility
0Cited by
7References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2002 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | May 23, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/041
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
Techniques include heating a substantially uniformly boron-doped wafer to achieve a significantly increased resistivity in a near-surface region of the wafer and forming at least one electrical circuit element in the near-surface region. Integrated circuits or other devices may include a semiconductor wafer with a substantially uniformly boron-doped bulk region and a reduced boron concentration layer near a surface of the wafer. An electrical circuit element may be provided in the reduced boron concentration layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.