Reading circuit for a non-volatile memory
US6667908B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2002 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | Jun 5, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reading circuit for a memory includes a current detector for each bit line of the memory, a reference voltage generator, and a comparator that compares the reference voltage with the voltage of a reading terminal of the current detector. Each current detector includes a first transistor whose gate is selectively connected to the reading terminal, and whose drain-source path is in series with a respective bit line. An input of a first inverter stage is connected to the source of the first transistor, and an output thereof is connected to the gate of the first transistor. The circuit has a very short reading time based upon each of the current detectors including a first resistor between the source of the first transistor and the bit line, along with second and third transistors having their drain-source paths connected in series with the respective bit line, and along with second and third inverters connected to the respective bit line. First and second resistive elements are also connected between the first and second transistors and the respective bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.