RAM data array configured to provide data-independent, write cycle coherent current drain
US6667923B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2002 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | Jul 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for forming a RAM data memory that generates predictable noise/interference components that are coherent with each write cycle and essentially independent of the data content of the RAM data memory. The RAM data memory is comprised of a plurality of cells, each representing a data bit, which are selectively addressable as memory bytes formed of multiple bits. Each cell is formed of two sets of cross-coupled transistors. By causing each set of cross-coupled transistors to be set to a common voltage level at the beginning of a write cycle before setting one set of transistors to a low level and the one set of transistors to be set to a high level (thus representing a desired data bit value), the associated noise/interference components of the power drain are data independent. Furthermore, the data-independent noise occurs at frequencies at or above the write cycle rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.