POS-PHY interface for interconnection of physical layer devices and link layer devices
US6668297B1 · kind B1 · utility
26Cited by
15References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1999 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | Dec 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J2203/0089
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A POS-PHY interface for interfacing between SONET/SDH PHY devices and Link Layer devices, including a 32 bit and an 8-bit point-to-point bus interface having a double-word data format operative to accommodate variable size packets of packet data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.