Memory-mounting integrated circuit and test method thereof
US6668348B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 2000 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | Jul 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To provide such a memory-mounting integrated circuit as well as a memory test method that can reduce costs to incur for a tester, regulate the number of the input-output terminals for testing, and nevertheless can monitor from outside all the contents of defects in principle. The memory-mounting integrated circuit on which at least a BIST circuit and a memory are mounted, in which the above described BIST circuit includes a data storing apparatus to store the data in a normal memory, a comparing apparatus to compare a memory test result signal from the above described memory with data from the above described data storing apparatus to output a first comparing signal, a control apparatus to control to implement outputting outward from the first comparing signal outputted by the above described comparing apparatus, and an output apparatus to output defective data outward by the above described control apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.