Methods and apparatuses for designing integrated circuits
US6668364B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2002 |
| Grant date | Dec 23, 2003 |
| Priority date | — |
| Expiry date | Jun 3, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for designing a plurality of integrated circuits (ICs) from a language representation of hardware. In one example of a method, a technology independent RTL (register transfer level) netlist is partitioned between representations of a plurality of ICs. In a typical example of the method, a hardware description language (HDL) code is written and compiled without regard to splitting the design among multiple ICs. After compilation, a partition of the technology independent RTL netlist, obtained from the compilation, is performed among the multiple ICs. After a partition, the technology independent RTh netlist is mapped to a particular target technology (e.g. a particular IC vendor's architecture for implementing logic circuitry), and place and route tools may be used to create the design in multiple ICs (e.g. field programmable gate arrays). Other examples of methods and apparatuses are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.