Method of aligning features in a multi-layer electrical connective device
US6668448B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2001 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Dec 8, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/5313
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of constructing an electric apparatus, comprising the following steps. First, a set of dielectric layers is provided. Next, a set of conductive features and at least one fiducial marking are formed on a first one of the dielectric layers, in mutual reference to each other so that their relative positions are known to a first tolerance. Then, a set of pin holes is formed in each dielectric layer, each pin hole formed in relation to the fiducial marking for its dielectric layer and all of the sets of pin holes having a mutually identical placement. Finally the dielectric layers are arranged onto a pin fixture having a set of pins that match the mutually identical placement of the pin holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.