Planarizing method for fabricating gate electrodes
US6670226B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2002 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Mar 8, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication, there is employed a planarizing method for forming, in a self aligned fashion, a patterned second gate electrode material layer laterally adjacent but not over a patterned first gate electrode material layer, such that upon further patterning of the patterned first gate electrode material layer and the patterned second gate electrode material layer there may be formed a first gate electrode over a first active region of a semiconductor substrate and a second gate electrode over a laterally adjacent second active region of the semiconductor substrate. The method is particularly useful within the context of complementary metal oxide semiconductor (CMOS) semiconductor integrated circuit microelectronic fabrications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.