Semiconductor device having ESD protective transistor
US6670678B2 · kind B2 · utility
7Cited by
1References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2003 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Feb 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
An insulation trench is formed between a drain region formed in a p-type well and a substrate contact region of GG NMOS transistor. The insulation trench extends deeper than the thickness of the p-type well and reaches the p-type substrate of the transistor. This configuration provides a parasitic BJT of the ESD protection transistor with an improves TLP characteristic, and facilitates the operation of the parasitic BJT of the GG MOS transistor accordingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.