Isolating circuit for P/N transmission gate during hot-plug insertion
US6670829B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 2002 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Jul 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bus switch has a p-channel and an n-channel transistor in parallel between two buses. When power is disconnected to the bus switch, and one bus is hot and has a voltage above ground, this higher voltage is conducted to the gate and substrate of the p-channel transistor. This biasing keeps the p-channel transistor turned off. A gate connecting p-channel transistor connects the hot bus to the p-channel gate node, while a substrate connecting p-channel transistor connects the hot bus to the substrate under the p-channel transistor. A third connecting p-channel transistor connects the hot bus to a power-down node. The power-down node is normally driven low through a delay line when power is applied. The power-down node is applied to the gate of a source transistor that connects power to the substrate and to an inverter that normally drives the p-channel gate node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.