Input clamp circuit for 5V tolerant and back-drive protection of I/O receivers using CMOS process
US6670840B1 · kind B1 · utility
3Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2002 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Jul 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a receiver input back-drive protection circuit and method, a pass gate is provided between the high pad voltage and the receiver input and a clamping circuit is provided, to present a reduced voltage to the receiver input during stress mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.