Data recovery circuit and method thereof
US6670853B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2002 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Jun 13, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data recovery circuit and a method thereof, which are capable of reducing locking time and jitter, are provided. The data recovery circuit includes a frequency-locked loop, a locking detector, a delay-locked loop, and a data determination circuit. The frequency-locked loop locks the frequency of an internal clock signal fed back thereto in response to an input signal with the frequency of the input signal and generates a frequency locking signal representing that the input signal is frequency-locked with the internal clock signal. The locking detector determines whether the frequency of the internal clock signal is in a predetermined frequency range of the input signal in response to the frequency locking signal and generates a phase control signal. The delay-locked loop is controlled by the phase control signal, locks the phase of the internal clock signal with the phase of the input signal, and generates a recovery locking signal. The data determination circuit receives the recovery locking signal as a clock signal, receives the input signal in response to the clock signal, and outputs the input signal as output data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.