VSB receiver
US6671002B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2000 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Aug 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/211
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The loop gain of an AGC circuit 7 and the loop gain of a clock regenerating circuit 6 are increased (the gain of an amplifier is increased, or the band of a loop filter is widened) until a synchronizing signal (a segment synchronizing signal or a field synchronizing signal) is detected. The loop gain of the AGC circuit 7 and the loop gain of the clock regenerating circuit 6 are decreased (the gain of the amplifier is decreased, or the band of the loop filter is narrowed) after the synchronizing signal is detected.Consequently, it is possible to make a reduction of a time period required until convergence processing is completed in the AGC circuit and the clock regenerating circuit compatible with an improvement of a ghost disturbance removal performance and accurate clock regeneration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.