Register stack in cache memory
US6671196B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2002 |
| Grant date | Dec 30, 2003 |
| Priority date | — |
| Expiry date | Jun 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CPU includes a register file including a plurality of architectural registers for storing data loaded from a primary memory for execution by the CPU. A stack cache memory coupled to the register file includes a plurality of cache lines, each of which corresponds to one of the architectural registers and implements a first-in, last-out queue for data spilled from the corresponding architectural register. Data spilled from the register file into the stack cache memory is maintained in the stack cache until subsequently restored to the register file without accessing primary memory. The stack cache memory does not participate in cache writeback operations to primary memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.